The semiconductor integrated circuit (IC) industry has experienced rapid growth. Over the course of this growth, functional density of the devices has generally increased while the device feature size or geometry has decreased. This scaling down process generally provides benefits by increasing production efficiency, lowering costs, and/or improving performance. Such scaling down has also increased the complexities of processing and manufacturing ICs and, for these advances to be realized similar developments in IC fabrication are needed.
Semiconductor ICs include devices such as transistors, capacitors, resistors, and inductors that are formed in or on the substrate of an IC using lithography and patterning techniques. These semiconductor devices are inter-connected according to the design of the IC to implement different functions. In a typical IC, the silicon area is divided into many regions for different functions. Due to the nature of different designs entailed by the different functions, some functional regions have a higher pattern density than other regions. For example, a region of the IC used for static random access memory (SRAM) may have a higher pattern density than a region for a logic function. The difference in pattern density may cause an undesirable “loading effect”. For example, a polysilicon layer formed on the substrate may be thicker in regions with high pattern density than regions with low pattern density. The unevenness, or topography, of the polysilicon layer may adversely affect the IC manufacturing process. There is a need in the art to address the loading effect caused by non-uniform pattern densities.